From 1783473a6c54140cb9243cae1175b008cd20e96f Mon Sep 17 00:00:00 2001 From: Luxferre Date: Thu, 18 Jun 2026 14:01:36 +0300 Subject: [PATCH] init upload --- Makefile | 22 ++ README.md | 66 +++++ amach | 4 + amach.awk | 357 ++++++++++++++++++++++ rv32ima_tests.bin | Bin 0 -> 15492 bytes rv32ima_tests.s | 741 ++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 1190 insertions(+) create mode 100644 Makefile create mode 100644 README.md create mode 100755 amach create mode 100644 amach.awk create mode 100755 rv32ima_tests.bin create mode 100644 rv32ima_tests.s diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..7a37a0a --- /dev/null +++ b/Makefile @@ -0,0 +1,22 @@ +CC = riscv64-linux-gnu-gcc +OBJCOPY = riscv64-linux-gnu-objcopy +EMULATOR = ./amach + +ASFLAGS = -march=rv32ima -mabi=ilp32 -nostdlib -static -fno-pic -fno-pie -mno-relax +LDFLAGS = -Wl,-Ttext=0x100b0 -Wl,--build-id=none + +all: rv32ima_tests.bin + +rv32ima_tests.elf: rv32ima_tests.s + $(CC) $(ASFLAGS) $(LDFLAGS) rv32ima_tests.s -o rv32ima_tests.elf + +rv32ima_tests.bin: rv32ima_tests.elf + $(OBJCOPY) -O binary rv32ima_tests.elf rv32ima_tests.bin + +run: rv32ima_tests.bin + $(EMULATOR) rv32ima_tests.bin + +clean: + rm -f rv32ima_tests.elf rv32ima_tests.bin + +.PHONY: all run clean diff --git a/README.md b/README.md new file mode 100644 index 0000000..c845471 --- /dev/null +++ b/README.md @@ -0,0 +1,66 @@ +# A-machine: a minimal RISC-V (RV32IMA) emulator in POSIX AWK + +## About + +A-machine is a simple and straightforward implementation of the RV32I specification with M (multiplication/division) and A (atomic operations) extenstions. It consists of two files: + +- [amach.awk](amach.awk), the emulator core itself that supports .dec files, +- and [amach](amach) shell script which is a two-liner that uses POSIX `od` to convert .bin files into .dec files on the fly and then passes them to the emulator core. + +Additionally, A-machine is shipped with a reference test suite that assumes that you have a full RISC-V toolchain installed under the `riscv64-linux-gnu-` prefix (adjustable in the `Makefile`). Just run `make run` to build and run all tests. In case you don't have any toolchain available, a file called `rv32ima_tests.bin` is also included into the repo. + +The project is to be considered highly experimental and not production-ready in any way. + +## Usage + +First, decide where your program needs to be loaded in memory. The default LVA (loading virtual address) is 0x100b0. In most AWK implementations, you need to convert this value to decimal (the default is 65712). + +Then, most probably, you'll want to use the provided wrapper: +```sh +[LVA=...] ./amach path/to/program.bin +``` + +Or you can run the following: +```sh +od -An -v -tu1 path/to/program.bin | POSIXLY_CORRECT=1 awk -f amach.awk [-v LVA=...] +``` + +But in case you already have a program in the `.dec` format, you can pass it directly to AWK: +```sh +POSIXLY_CORRECT=1 awk -f amach.awk [-v LVA=...] -- path/to/program.dec +``` + +## Support + +Currently, A-machine only supports the **unprivileged** RV32IMA instruction set with a few additional `ecall` syscalls: 63 (sys_read, for fd 0 only), 64 (sys_write, for fd 1 and 2 only) and 93 (sys_exit). For completeness, `fence` instruction is also supported but yields a no-op. + +## Plans (from higher to lower priority) + +- Implement the C-extension (compressed instruction set). +- Implement a simple RV32IMAC disassembler in POSIX AWK. +- Introduce more popular Linux-compatible syscalls (that make sense to implement in AWK but don't increase the overall project complexity). +- Test for RV32EMC compatibility (that the code built for the "embedded" variant runs here). +- Implement a privileged instruction set minimum (Zicsr), interrupts and traps. +- If time permits, implement a simple RV32IMAC assembler in POSIX AWK, with full pseudo-instruction support. + +## FAQ + +### What was the rationale of creating a platform emulator in the least suitable language for this purpose? + +The main reason is maximum portability. While AWK is clearly tailored for text processing and, in its standard variant, doesn't even has bitwise operations and hexadecimal literals support, it still remains the single most common scripting language present on every POSIX-compatible system, including embedded ones that run [BusyBox](https://busybox.net/) on top of the kernel and might not have anything else from available programming tools at all. In such conditions, an emulation layer written in AWK is far from efficient but still better than nothing. + +Apart from that, the A-machine serves more of an educational purpose for the author to learn about the RISC-V ISA and the details of its inner workings. + +### Will I be able to run a Linux kernel on A-machine? + +While A-Machine creation was partially inspired by the wonderful [mini-rv32ima project](https://github.com/cnlohr/mini-rv32ima) (although not a single line of code had been taken from there), running a (no-MMU) Linux kernel here is not currently possible due to several reasons. First, A-machine needs to support Zicsr and other privileged RV32 extensions to even theoretically be capable of running the kernel. Second, in order to run the same kernel build as mini-rv32ima does, A-machine will need to support the exact same MMIO model and non-standard CSR calls as mini-rv32ima, which already is non-trivial and will indeed require some logic copy-pasting, which the author is trying to avoid. + +So, the answer is: no, not anytime soon. + +### 64 bits, floats, doubles? + +Not in this project. As already mentioned, A-machine, as well as all of its supplementary artifacts, is more of educational value. Stay tuned for the next RISC-V-related emulation projects for something more practical, fast and powerful. + +## Credits + +Created by Luxferre in 2026, released into the public domain with no warranties. diff --git a/amach b/amach new file mode 100755 index 0000000..0a586db --- /dev/null +++ b/amach @@ -0,0 +1,4 @@ +#!/bin/sh +# A-Machine .bin launcher wrapper +[ -z "$LVA" ] && LVA=65712 # 0x100b0 +od -An -v -tu1 "$1" | POSIXLY_CORRECT=1 awk -f amach.awk -v LVA="$LVA" diff --git a/amach.awk b/amach.awk new file mode 100644 index 0000000..9ab84e1 --- /dev/null +++ b/amach.awk @@ -0,0 +1,357 @@ +#!/usr/bin/env awk -f +# A-Machine: an experimental RISC-V (RV32IMA) emulator in POSIX AWK +# with a very small subset of supported ECALLs +# Accepts a headerless binary previously converted to .dec format +# e.g. with POSIX od: od -An -v -tu1 program.bin > program.dec +# Usage: awk -f amach.awk [-v LVA=...] -- prog.dec +# Or run a .bin directly with: +# od -An -v -tu1 program.bin | awk -f amach.awk [-v LVA=...] +# Created by Luxferre in 2026, released into the public domain + +# fatal error reporting function +function trapout(msg) { + cmd = "cat 1>&2" + printf("Fatal: %s\n", msg) | cmd + close(cmd) + exit(1) +} + +# helper functions + +function setreg(idx, val) { + if(idx > 0) { + val = int(val) % 4294967296 + if(val < 0) val += 4294967296 + REG[idx] = (val >= 2147483648) ? (val - 4294967296) : val + } +} + +function getreg(idx) {return (idx == 0) ? 0 : int(REG[idx])} + +function imm_sign_ex(val) {val = int(val); return (val >= 2048) ? (val - 4096) : val} +function imm_sign_ex_b(val) {val = int(val); return (val >= 4096) ? (val - 8192) : val} + +function floor(x, i) { + i = int(x) + return (x >= 0 || x == i) ? i : (i - 1) +} + +function ord(c, b) { + if(!TGL_ORD["#"]) for(b=0;b<256;b++) TGL_ORD[sprintf("%c", b)] = b + return int(TGL_ORD[c]) +} + +function bw_and(a, b, v, r) { + v = 1; r = 0 + a = int(a) + b = int(b) + if(a < 0) a += 4294967296 + if(b < 0) b += 4294967296 + while(a > 0 || b > 0) { + if((a%2) == 1 && (b%2) == 1) r += v + a = int(a/2) + b = int(b/2) + v *= 2 + } + return int(r) +} + +function bw_or(a, b, v, r) { + v = 1; r = 0 + a = int(a) + b = int(b) + if(a < 0) a += 4294967296 + if(b < 0) b += 4294967296 + while(a > 0 || b > 0) { + if((a%2) == 1 || (b%2) == 1) r += v + a = int(a/2) + b = int(b/2) + v *= 2 + } + return int(r) +} + +function bw_xor(a, b, v, r) { + v = 1; r = 0 + a = int(a) + b = int(b) + if(a < 0) a += 4294967296 + if(b < 0) b += 4294967296 + while(a > 0 || b > 0) { + if((a%2) != (b%2)) r += v + a = int(a/2) + b = int(b/2) + v *= 2 + } + return int(r) +} + +function read_word(addr, val) { + addr = int(addr) % 4294967296 + if(addr < 0) addr += 4294967296 + val = MEM[addr] + MEM[(addr+1)%4294967296]*256 + MEM[(addr+2)%4294967296]*65536 + MEM[(addr+3)%4294967296]*16777216 + return (val >= 2147483648) ? (val - 4294967296) : val +} + +function write_word(addr, val) { + addr = int(addr) % 4294967296 + if(addr < 0) addr += 4294967296 + val = int(val) % 4294967296 + if(val < 0) val += 4294967296 + MEM[addr] = val % 256 + MEM[(addr+1)%4294967296] = int(val/256) % 256 + MEM[(addr+2)%4294967296] = int(val/65536) % 256 + MEM[(addr+3)%4294967296] = int(val/16777216) % 256 +} + +# syscall emulation + +function handle_ecall(callnum, a0, a1, a2, a3, a4, a5, i, l, buf, addr) { + if(callnum == 63) { # sys_read + if(a0 == 0) { + getline buf < "/dev/tty" + l = length(buf) + if(l > a2) l = a2 + for(i=0;i= 0) ? r1 : (r1 + 4294967296) + ur2 = (r2 >= 0) ? r2 : (r2 + 4294967296) + shamt = ur2 % 32 + + if(f3 == 0 && f7 == 0) setreg(rd, r1 + r2) + else if(f3 == 0 && f7 == 32) setreg(rd, r1 - r2) + else if(f3 == 4 && f7 == 0) setreg(rd, bw_xor(r1, r2)) + else if(f3 == 6 && f7 == 0) setreg(rd, bw_or(r1, r2)) + else if(f3 == 7 && f7 == 0) setreg(rd, bw_and(r1, r2)) + else if(f3 == 1 && f7 == 0) setreg(rd, (r1 * (2^shamt)) % 4294967296) + else if(f3 == 5 && f7 == 0) setreg(rd, int(ur1 / (2^shamt))) + else if(f3 == 5 && f7 == 32) setreg(rd, floor(r1 / (2^shamt))) + else if(f3 == 2 && f7 == 0) setreg(rd, (r1 < r2) ? 1 : 0) + else if(f3 == 3 && f7 == 0) setreg(rd, (ur1 < ur2) ? 1 : 0) + else if(f3 == 0 && f7 == 1) setreg(rd, (r1 * r2) % 4294967296) + else if(f3 == 1 && f7 == 1) setreg(rd, floor((r1 * r2) / 4294967296)) + else if(f3 == 2 && f7 == 1) setreg(rd, floor((r1 * ur2) / 4294967296)) + else if(f3 == 3 && f7 == 1) setreg(rd, floor((ur1 * ur2) / 4294967296)) + else if(f3 == 4 && f7 == 1) setreg(rd, (r2 == 0) ? -1 : int(r1 / r2)) + else if(f3 == 5 && f7 == 1) setreg(rd, (r2 == 0) ? 4294967295 : int(ur1 / ur2)) + else if(f3 == 6 && f7 == 1) setreg(rd, (r2 == 0) ? r1 : (r1 % r2)) + else if(f3 == 7 && f7 == 1) setreg(rd, (r2 == 0) ? r1 : (ur1 % ur2)) + else trapout(sprintf("Illegal instruction at 0x%X", pc-4)) +} + +function amach_store(f3, rs1, rs2, immval, r1, r2, base) { + r1 = getreg(rs1) + r2 = getreg(rs2) + if(r2 < 0) r2 += 4294967296 + base = (r1 + immval) % 4294967296 + if(base < 0) base += 4294967296 + if(f3 == 0) MEM[base] = r2 % 256 + else if(f3 == 1) { + MEM[base] = r2 % 256 + MEM[(base + 1)%4294967296] = int(r2/256) % 256 + } + else if(f3 == 2) { + MEM[base] = r2 % 256 + MEM[(base + 1)%4294967296] = int(r2/256) % 256 + MEM[(base + 2)%4294967296] = int(r2/65536) % 256 + MEM[(base + 3)%4294967296] = int(r2/16777216) % 256 + } + else trapout(sprintf("Illegal instruction at 0x%X", pc-4)) +} + +function amach_branch(f3, rs1, rs2, immval, r1, r2, ur1, ur2, taken) { + r1 = getreg(rs1) + r2 = getreg(rs2) + ur1 = (r1 >= 0) ? r1 : (r1 + 4294967296) + ur2 = (r2 >= 0) ? r2 : (r2 + 4294967296) + taken = 0 + if(f3 == 0) taken = (r1 == r2) + else if(f3 == 1) taken = (r1 != r2) + else if(f3 == 4) taken = (r1 < r2) + else if(f3 == 5) taken = (r1 >= r2) + else if(f3 == 6) taken = (ur1 < ur2) + else if(f3 == 7) taken = (ur1 >= ur2) + else trapout(sprintf("Illegal instruction at 0x%X", pc-4)) + + if(taken) pc += immval + else pc += 4 +} + +function amach_imm(opcode, f3, rd, rs1, immval, r1, ur1, base, shamt, val) { + r1 = getreg(rs1) + ur1 = (r1 >= 0) ? r1 : (r1 + 4294967296) + if(opcode == 3) { # load + base = (r1 + immval) % 4294967296 + if(base < 0) base += 4294967296 + if(f3 == 0) { # lb + val = MEM[base] + setreg(rd, (val >= 128) ? (val - 256) : val) + } + else if(f3 == 1) { # lh + val = MEM[base] + MEM[(base+1)%4294967296]*256 + setreg(rd, (val >= 32768) ? (val - 65536) : val) + } + else if(f3 == 2) { + val = MEM[base] + MEM[(base+1)%4294967296]*256 + MEM[(base+2)%4294967296]*65536 + MEM[(base+3)%4294967296]*16777216 + setreg(rd, val) + } + else if(f3 == 4) setreg(rd, MEM[base]) # lbu + else if(f3 == 5) setreg(rd, MEM[base] + MEM[(base+1)%4294967296]*256) # lhu + else trapout(sprintf("Illegal instruction at 0x%X", pc-4)) + } else if(opcode == 19) { # 0x13, immediate arithmetic + shamt = bw_and(immval, 31) + if(f3 == 0) setreg(rd, r1 + immval) + else if(f3 == 4) setreg(rd, bw_xor(r1, immval)) + else if(f3 == 6) setreg(rd, bw_or(r1, immval)) + else if(f3 == 7) setreg(rd, bw_and(r1, immval)) + else if(f3 == 1) setreg(rd, (r1 * (2^shamt)) % 4294967296) # slli + else if(f3 == 5 && immval < 1024) setreg(rd, int(ur1 / (2^shamt))) # srli + else if(f3 == 5 && immval >= 1024) setreg(rd, floor(r1 / (2^shamt))) # srai + else if(f3 == 2) setreg(rd, (r1 < immval) ? 1 : 0) + else if(f3 == 3) setreg(rd, (ur1 < immval) ? 1 : 0) + else trapout(sprintf("Illegal instruction at 0x%X", pc-4)) + } else if(opcode == 103) { # 0x67, JALR + setreg(rd, pc) + pc = r1 + immval + } else if(opcode == 115) { # 0x73, system call / csr + if(immval == 0) handle_ecall(getreg(17), getreg(10), getreg(11), getreg(12), getreg(13), getreg(14), getreg(15)) + else trapout(sprintf("Unimplemented external system call at 0x%X", pc-4)) + } else trapout(sprintf("Illegal instruction at 0x%X", pc-4)) +} + +# A-extension +function amach_atomic(f3, f5, aq, rl, rd, rs1, rs2, r1, r2, val, uval, ur2) { + r1 = getreg(rs1) + r2 = getreg(rs2) + ur2 = (r2 >= 0) ? r2 : (r2 + 4294967296) + if(f3 == 2) { + val = read_word(r1) + uval = (val >= 0) ? val : (val + 4294967296) + if(f5 == 0) { # amoadd.w + setreg(rd, val) + write_word(r1, val + r2) + } else if(f5 == 1) { # amoswap.w + setreg(rd, val) + write_word(r1, r2) + } else if(f5 == 2) { # lr.w + setreg(rd, val) + RES_ADDR = r1 + } else if(f5 == 3) { # sc.w + if(RES_ADDR == r1) { + write_word(r1, r2) + setreg(rd, 0) + RES_ADDR = -1 + } else { + setreg(rd, 1) + } + } else if(f5 == 4) { # amoxor.w + setreg(rd, val) + write_word(r1, bw_xor(val, r2)) + } else if(f5 == 8) { # amoor.w + setreg(rd, val) + write_word(r1, bw_or(val, r2)) + } else if(f5 == 12) { # amoand.w + setreg(rd, val) + write_word(r1, bw_and(val, r2)) + } else if(f5 == 16) { # amomin.w + setreg(rd, val) + write_word(r1, val <= r2 ? val : r2) + } else if(f5 == 20) { # amomax.w + setreg(rd, val) + write_word(r1, val >= r2 ? val : r2) + } else if(f5 == 24) { # amominu.w + setreg(rd, val) + write_word(r1, uval <= ur2 ? val : r2) + } else if(f5 == 28) { # amomaxu.w + setreg(rd, val) + write_word(r1, uval >= ur2 ? val : r2) + } else trapout(sprintf("Unimplemented atomic instruction at 0x%X", pc-4)) + } else trapout(sprintf("Illegal atomic instruction at 0x%X", pc-4)) +} + +# main instruction decoding and execution routine +function amach_exec(instr, opcode, rd, rs1, rs2, imm, funct3, funct7) { + opcode = instr % 128 + instr = int(instr / 128) + rd = instr % 32 + imm = int(instr / 32) + funct3 = imm % 8 + rs1 = int(imm / 8) % 32 + rs2 = int(imm / 256) % 32 + funct7 = int(imm / 8192) + + if(opcode == 51) { # 0x33, register arithmetic, type R + amach_reg_arith(funct3, funct7, rd, rs1, rs2) + } else if(opcode == 47) { # 0x2f, atomic operations, type R + amach_atomic(funct3, int(funct7 / 4), int(funct7 / 2) % 2, funct7 % 2, rd, rs1, rs2) + } else if(opcode == 3 || opcode == 19 || opcode == 103 || opcode == 115) { # type I + amach_imm(opcode, funct3, rd, rs1, imm_sign_ex(rs2 + funct7 * 32)) + } else if(opcode == 35) { # 0x23, store, type S + amach_store(funct3, rs1, rs2, imm_sign_ex(rd + funct7 * 32)) + } else if(opcode == 99) { # 0x63, branch, type B + imm = rd + (funct7 % 64) * 32 + (rd % 2) * 2047 + int(funct7 / 64) * 4096 + pc -= 4 + amach_branch(funct3, rs1, rs2, imm_sign_ex_b(imm)) + } else if(opcode == 111) { # 0x6F, JAL, type J + setreg(rd, pc) + imm_10_1 = int(rs2 / 2) + (funct7 % 64) * 16 + imm_19_12 = funct3 + rs1 * 8 + imm = imm_10_1 * 2 + (rs2 % 2) * 2048 + imm_19_12 * 4096 + int(funct7 / 64) * 1048576 + if(imm >= 1048576) imm -= 2097152 + pc += imm - 4 + } else if(opcode == 55) { # 0x37, LUI, type U + setreg(rd, imm * 4096) + } else if(opcode == 23) { # 0x17, AUIPC, type U + setreg(rd, imm * 4096 + pc - 4) + } else if(opcode == 15) { # 0x0F, FENCE, type I / no-op + # no-op + } else trapout(sprintf("Illegal instruction at 0x%X", pc-4)) +} + +# Initialization section +BEGIN { + split("", MEM) # init the memory array + split("", REG) # init the (integer) registers + REG[0] = 0 # zero register + REG[2] = 2^31 # stack pointer top + RES_ADDR = -1 # reserved address for atomic ops + LVA = int(LVA) + pc = LVA +} + +# Decimal memory collection section +/^[[:space:]]*[[:digit:][:space:]]+/ {for(i=1; i<=NF; i++) MEM[pc++] = int($i)} + +# Execution section +END { + memsize = pc - LVA + pc = LVA + while(pc > -1) { + instr = MEM[pc++] + 256 * MEM[pc++] + if((instr % 4) == 3) # full instruction + instr += 65536 * MEM[pc++] + 16777216 * MEM[pc++] + amach_exec(instr) # decode and execute + } +} diff --git a/rv32ima_tests.bin b/rv32ima_tests.bin new file mode 100755 index 0000000000000000000000000000000000000000..e8889b767078d79ff42cf2038dc01a8e66a108f8 GIT binary patch literal 15492 zcmeI2k8@Pj702)H%dY(Jku{Gs_ybrHz+Zq6h*A8t{D?|*H4TIoTU|DrO$cnVVK*C) zk-D%zZSC6VPD-_{#wxYd>Cl!&>R8&fi2b>pR3}sIj4ds7?9@&ZO#_xH>ACmZefPYV z1^$6`#@U;5@BN(bIrqMM-@T8@0Aq%(zn)&GvutK2tM(mn7+OEeI#)Ri{kS8WakB8V zBaX^>(9Y#bX7}pMa36OJ`*NR+v6Q1y^bh=k_D5SjM{USFddAQo1ys~*{WwD*UZMOZ$>5qW@?pU>ffjRW&AHvo1sB2 z1=Fr`?|n+A{}#o}KTrE3Gw>a16S3D6jeUb+vKtgL^KIH+=JOe96FO^(#on||#hzQL zn1OH6{xYB6pticvkr6}F%Cjp+%j-UYvi=F?l^xM=u14#LB(+JM{)svdEL1w#B*n~ZrTvkqcTt4!BdXVp1&rPP^&d^!~~5T*TP zJ~vaFcy3{hIpj=0PA9C}b5Sd-+n$Dklf+PGG+#=^Yf?1}5_u~|}cYS`1e zO|kV5?UmbKPqRc? zH=f?8;_B-uL+V{eZQ|L|8rY!xseOcnaA^a#m&@HhSa;7+QfR!$E_&W>rmX@^@^+eDMRYL zh1yKLHO2ILKUQ4NrxiD|oHC@|8>r3HE4cRk*LzCl7xK`1r{e0hlp*ylrMAKve%L54 z&!$I54z1+6M{Msm2R=al2%m5Dgnun%N&Z4=6KfBjZ;i$Bao}GhAAZHnTtyi&A6HVF znMD~=?@VfwT&}km z_Z`LUy;gDcODIF?t)#XIz7pkZx-QAqJ1ULO>O&~4pynbUacJ+KeW3U za_z9K$z#95TsuJP;0(nMI4K9&c}8u+&Kz(VgFf);I#+{lLwp)2EG$X46~$b7bmVFWL74r)Ynvcg$iFd06Fm&k0PaJ6q5Ve$<($?`5UC z_X4F`|G>f%?=YERi)|X@dfKC>4SkwTw|7A4ZXoXg`S&gT1vBtZi%sa(K=-Qi=uRF~ zy4izDcjjFS58u81PHnhO_p`7&0p~;<)2vgDsbvoz`=0WVODZ3Mzfhjc|2x!H*bC5y zN6Z`UYvMlE^qlgMiYXuZ+mwesGJm8t)5pc|`A33t;2VSQy< z$h)4@1rYzGgqNm$C2u#irB@c?H8tVb37%K*7V;eBzd-vQPBT{Rf$_pR%XweqH8ZZ> zt%c6M1`+$dad@}Rl`C%G0m_xUZPX_6nIZ3Df|tAtdHh{0H-+%JXYZMqe?sSAhM;10zNv`~ih)l6-;9+})x8+W_K+eWu9voPVTzD5{4VzUS@@pwW z>TRSpGY^7G&Vu+{U4vXWOR&Kf#SPp|8B*_E)Mj$4xL!N=*nGup2r6#=4$6>vZ>Kgq zTlv_bnqqkvo1^kDxIu9Pt0+V2T|sSlx3iJKnHcmgR`0hW58j!`UCi^lPI2=$Q-;)g z6SWyy?o3uIa0hMcfp-RS2YG(+&L8K)^^_s?UPo=Hmr1?${CW+N-!(*U4P{8ZOQ;R= zJ2KAmV7WUJd1#u(x#AlI8^rw|^;+%$q~2>N*UWEYvHTvGO!ABO|MwVeN@ z-v3&;GQWar&u_iBGcw#FzZWWQ-g*a6&EF+goy=~R*2W8$93aPvJ*p8tg&>-isIhi}4gZ#B*DI9PRbvW)+PmECW9-n_q&dV%flA$qOn zevJRml!fv0@uKk$9aGPPe=FhriT1T=mG4A>w`d#7cLp(5Lph~2wMDV@A=(e)&b&!& zsP(u_>)xLt55BdqR4d^P(!TV3Qa7u-+?aM|1oAsa<~L8<7C)y9yu|&O=Mef0Q!L5<^J(vz+&f$1wDw zH3s?pU(5^J_kWz5uTcLY2E7c{`^-jb46f$|*9~>r>Vkyx+uefI9cdQ^PE`LU99@y8w6}8pmg} zpTQj3CG-DX>c{dOOw9X%uW`QNhVNjE-K5yoI{;+q&ruf6d;VRGKBLLU2@mf8aLg=s z0O}dtIIgtnPf`BFXEd2Xc0XTF@a!+xdF$C<*aA;bR&lMhUs78A3smg+KHAro*JtGT zS?&NP=CyW@VyEUSw%$wG$jVsG{iv0%r82KB*neE_KBQt#%^|!;D9@(#Rmp#twy|gx z?4cb>Ywj||4(z4rq;B7ZYBJ@@!iFS~*kP1?;44CTi{5s}-nRf-|eM8xF^r>O~i^>IJ)4_0^BD>MQ3sj4~I??r||=vRn3>2kT(U zZMe!nH*=$pWDxwj4A*4-Tunin7i_G|*elviHeBMFb4&d#T%(~Gth&FMrG2kDw7I(+ z>A5Q$+Eoq*=y0~BU@RSu@#^`YXYMY>b!hcvEIi4@^98!5v)IV&ap=pSFK_EG`>&nScEk7>gr!ILqT)3Rl|;G0T6eBbPLE=_bh;hs^ePPG7gIy3e- z*@@|8XSg5j802nb_Gs3*i=FuTI*ZRjjzTRh?ZK{Cf{8+BqzwzPo=Chk8r#Ma(eCzO zv>SihN~*D-5zB#3DLG zlNd=T+1?cvmd&APusI&;3~yq*7;W#|!V7U?j1z0DwKWmxX3deU!S2wONT(=u#<~lC zbw)^u*dZX<9!kXCX10eCu}2|dvjYUJJhVm38eUX2(O9S@xGffMVWPAt6m3cSPWy?C`S5gFljmmIx7+Lfd$xL)7wL&f&kb&g4J^azsHkO`2^J z;b0;e4o4CR21POb!@<^2J46@@M&m5h5ld_fbp>P57PH(L*~ZK8C>G4TD6M?1%Er7{ zXbTfkTKU|RR@GFs>}c=gEthZ)ybMjvGT3W~9m}EZ1#$-zB^i1qO*1bS?4j+-&dc1s zcuCFDWwqDUU4KKUIouLyWj^0+E7sh#+{YI9BHOzn;qFL_Z}E2ct1Z^e3-#M0;UqUQ zUw0(Yoq(3Uu23QoX;}azp1nxRqA6@eG>Y}Uh81hq)~}v3g{_TsM5K+os9z1uO8=EI nP|83l1Ema