added C-extension support
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Luxferre
@@ -1,5 +1,5 @@
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#!/usr/bin/env awk -f
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# A-Machine: an experimental RISC-V (RV32IMA) emulator in POSIX AWK
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# A-Machine: an experimental RISC-V (RV32IMAC) emulator in POSIX AWK
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# with a very small subset of supported ECALLs
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# Accepts a headerless binary previously converted to .dec format
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# e.g. with POSIX od: od -An -v -tu1 program.bin > program.dec
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@@ -275,8 +275,148 @@ function amach_atomic(f3, f5, aq, rl, rd, rs1, rs2, r1, r2, val, uval, ur2) {
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} else trapout(sprintf("Illegal atomic instruction at 0x%X", pc-4))
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}
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# C-extension (compressed instructions) handler
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function amach_comp(instr, op, f3, b12, r11_7, r9_7, r6_2, r4_2, shamt, imm, base, val) {
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op = instr % 4
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f3 = int(instr / 8192) % 8
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b12 = int(instr / 4096) % 2
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r11_7 = int(instr / 128) % 32
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r9_7 = (int(instr / 128) % 8) + 8
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r6_2 = int(instr / 4) % 32
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r4_2 = (int(instr / 4) % 8) + 8
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shamt = r6_2 + b12 * 32
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if (op == 0) {
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if (f3 == 0) { # C.ADDI4SPN
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imm = (int(instr / 128) % 16) * 64 + (int(instr / 2048) % 4) * 16 + (int(instr / 32) % 2) * 8 + (int(instr / 64) % 2) * 4
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if (imm == 0) trapout(sprintf("Illegal instruction C.ADDI4SPN at 0x%X", pc-2))
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setreg(r4_2, getreg(2) + imm)
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} else if (f3 == 2) { # C.LW
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imm = (int(instr / 32) % 2) * 64 + (int(instr / 1024) % 8) * 8 + (int(instr / 64) % 2) * 4
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base = (getreg(r9_7) + imm) % 4294967296
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if (base < 0) base += 4294967296
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val = MEM[base] + MEM[(base+1)%4294967296]*256 + MEM[(base+2)%4294967296]*65536 + MEM[(base+3)%4294967296]*16777216
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setreg(r4_2, val)
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} else if (f3 == 6) { # C.SW
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imm = (int(instr / 32) % 2) * 64 + (int(instr / 1024) % 8) * 8 + (int(instr / 64) % 2) * 4
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base = (getreg(r9_7) + imm) % 4294967296
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if (base < 0) base += 4294967296
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val = getreg(r4_2)
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if (val < 0) val += 4294967296
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MEM[base] = val % 256
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MEM[(base+1)%4294967296] = int(val/256) % 256
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MEM[(base+2)%4294967296] = int(val/65536) % 256
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MEM[(base+3)%4294967296] = int(val/16777216) % 256
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} else trapout(sprintf("Illegal instruction at 0x%X", pc-2))
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} else if (op == 1) {
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if (f3 == 0) { # C.NOP / C.ADDI
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imm = r6_2 + b12 * 32
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if (imm >= 32) imm -= 64
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setreg(r11_7, getreg(r11_7) + imm)
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} else if (f3 == 1 || f3 == 5) { # C.JAL / C.J
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imm = b12 * 2048 + (int(instr / 256) % 2) * 1024 + (int(instr / 512) % 4) * 256 + (int(instr / 64) % 2) * 128 + (int(instr / 128) % 2) * 64 + (int(instr / 4) % 2) * 32 + (int(instr / 2048) % 2) * 16 + (int(instr / 8) % 8) * 2
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if (imm >= 2048) imm -= 4096
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if (f3 == 1) setreg(1, pc)
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pc = (pc - 2) + imm
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} else if (f3 == 2) { # C.LI
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imm = r6_2 + b12 * 32
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if (imm >= 32) imm -= 64
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setreg(r11_7, imm)
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} else if (f3 == 3) { # C.ADDI16SP / C.LUI
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if (r11_7 == 2) { # C.ADDI16SP
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imm = b12 * 512 + (int(instr / 8) % 4) * 128 + (int(instr / 32) % 2) * 64 + (int(instr / 4) % 2) * 32 + (int(instr / 64) % 2) * 16
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if (imm >= 512) imm -= 1024
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if (imm == 0) trapout(sprintf("Illegal instruction C.ADDI16SP at 0x%X", pc-2))
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setreg(2, getreg(2) + imm)
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} else if (r11_7 != 0) { # C.LUI
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imm = r6_2 + b12 * 32
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if (imm >= 32) imm -= 64
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imm = imm * 4096
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if (imm == 0) trapout(sprintf("Illegal instruction C.LUI at 0x%X", pc-2))
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setreg(r11_7, imm)
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}
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} else if (f3 == 4) {
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val = int(instr / 1024) % 4
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if (val == 0) { # C.SRLI
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if (shamt >= 32) trapout(sprintf("Illegal shift amount %d at 0x%X", shamt, pc-2))
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imm = getreg(r9_7)
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if (imm < 0) imm += 4294967296
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setreg(r9_7, int(imm / (2^shamt)))
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} else if (val == 1) { # C.SRAI
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if (shamt >= 32) trapout(sprintf("Illegal shift amount %d at 0x%X", shamt, pc-2))
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setreg(r9_7, floor(getreg(r9_7) / (2^shamt)))
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} else if (val == 2) { # C.ANDI
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imm = r6_2 + b12 * 32
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if (imm >= 32) imm -= 64
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setreg(r9_7, bw_and(getreg(r9_7), imm))
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} else if (val == 3) { # C.SUB, C.XOR, C.OR, C.AND
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imm = int(instr / 32) % 4
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if (b12 != 0) trapout(sprintf("Illegal register-register instruction at 0x%X", pc-2))
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if (imm == 0) setreg(r9_7, getreg(r9_7) - getreg(r4_2))
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else if (imm == 1) setreg(r9_7, bw_xor(getreg(r9_7), getreg(r4_2)))
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else if (imm == 2) setreg(r9_7, bw_or(getreg(r9_7), getreg(r4_2)))
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else if (imm == 3) setreg(r9_7, bw_and(getreg(r9_7), getreg(r4_2)))
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}
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} else if (f3 == 6 || f3 == 7) { # C.BEQZ / C.BNEZ
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imm = b12 * 256 + (int(instr / 32) % 4) * 64 + (int(instr / 4) % 2) * 32 + (int(instr / 1024) % 4) * 8 + (int(instr / 8) % 4) * 2
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if (imm >= 256) imm -= 512
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val = (f3 == 6) ? (getreg(r9_7) == 0) : (getreg(r9_7) != 0)
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pc = val ? (pc - 2) + imm : pc
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}
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} else if (op == 2) {
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if (f3 == 0) { # C.SLLI
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if (shamt >= 32) trapout(sprintf("Illegal shift amount %d at 0x%X", shamt, pc-2))
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if (r11_7 != 0) {
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setreg(r11_7, (getreg(r11_7) * (2^shamt)) % 4294967296)
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}
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} else if (f3 == 2) { # C.LWSP
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if (r11_7 == 0) trapout(sprintf("Illegal instruction C.LWSP with rd=0 at 0x%X", pc-2))
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imm = (int(instr / 4) % 4) * 64 + b12 * 32 + (int(instr / 16) % 8) * 4
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base = (getreg(2) + imm) % 4294967296
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if (base < 0) base += 4294967296
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val = MEM[base] + MEM[(base+1)%4294967296]*256 + MEM[(base+2)%4294967296]*65536 + MEM[(base+3)%4294967296]*16777216
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setreg(r11_7, val)
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} else if (f3 == 4) { # C.JR, C.MV, C.JALR, C.ADD
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if (b12 == 0) {
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if (r6_2 == 0) { # C.JR
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if (r11_7 == 0) trapout(sprintf("Illegal instruction C.JR with rs1=0 at 0x%X", pc-2))
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pc = getreg(r11_7)
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} else { # C.MV
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setreg(r11_7, getreg(r6_2))
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}
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} else {
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if (r6_2 == 0) {
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if (r11_7 == 0) { # C.EBREAK
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trapout(sprintf("EBREAK at 0x%X", pc-2))
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} else { # C.JALR
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imm = getreg(r11_7)
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setreg(1, pc)
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pc = imm
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}
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} else { # C.ADD
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setreg(r11_7, getreg(r11_7) + getreg(r6_2))
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}
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}
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} else if (f3 == 6) { # C.SWSP
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imm = (int(instr / 128) % 4) * 64 + (int(instr / 512) % 16) * 4
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base = (getreg(2) + imm) % 4294967296
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if (base < 0) base += 4294967296
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val = getreg(r6_2)
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if (val < 0) val += 4294967296
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MEM[base] = val % 256
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MEM[(base+1)%4294967296] = int(val/256) % 256
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MEM[(base+2)%4294967296] = int(val/65536) % 256
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MEM[(base+3)%4294967296] = int(val/16777216) % 256
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} else trapout(sprintf("Illegal instruction at 0x%X", pc-2))
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} else trapout(sprintf("Illegal instruction at 0x%X", pc-2))
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}
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# main instruction decoding and execution routine
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function amach_exec(instr, opcode, rd, rs1, rs2, imm, funct3, funct7) {
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if ((instr % 4) != 3) {
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amach_comp(instr)
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return
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}
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opcode = instr % 128
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instr = int(instr / 128)
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rd = instr % 32
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